VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilo...
Copy the install, test the workflow, then decide if it earns a permanent slot.
Still active enough to matter. Good candidate for a fast stack test instead of a long evaluation loop.
Copy the install, test the workflow, then decide if it earns a permanent slot.
Not hard to test, not trivial to unwind. Worth trying if it closes a sharp gap.
GitHub health 28/100. no security policy. 0 open issues make this testable, but not something to trust blind.
AI Agent
Claude Code
Model
Claude
Fastest way to find out if veriflow-cc belongs in your setup.
Copy the install command, run a real test, and back it out cleanly if it slows you down.
# Visit: https://github.com/bjwanneng/veriflow-ccRun this first. You will know quickly if the workflow earns a permanent slot.
# No automated removal — visit https://github.com/bjwanneng/veriflow-ccNo messy cleanup loop. If it misses, remove it and keep moving.
Install Location
~/ └─ .claude/ ├─ commands/ ├─ agents/ │ └─ veriflow-cc/ ← installs here └─ settings.json
VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.
Source: GitHub repository
Source check: July 18, 2026
Upstream commit: July 9, 2026
Repository state: Not marked archived
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